1. Field of the Invention
This invention relates to DRAM (Dynamic Random-Access Memory) technology, and more particularly to a circuit for measuring the data retention time of a DRAM cell.
2. Description of Related Art
As DRAMs are fabricated to higher levels of integration, the data-storage capacitors in the DRAM are downsized to a level that reduces the data-retention capability thereof. In DRAM design and fabrication, the DRAM data retention time is an important factor that determines the reliability of the DRAM. The longer the retention time, the better the reliability of the DRAM is.
Therefore, during the fabrication of DRAM, measurement of the data retention time is required. A low data retention time causes error in data read when the DRAM is used to store data.
FIG. 1 is a schematic diagram of a conventional source-follower circuit which is an equivalent of a DRAM cell. As shown, the source-follower circuit includes an NMOS transistor 10 having a gate connected to an input voltage V.sub.in, a drain connected to a system voltage VC, and a source connected via a load resistor 12 to a second system voltage VS. The load resistor 12 allows the output voltage V.sub.out at the source of the NMOS transistor 10 to follow the input voltage V.sub.in at the gate of the NMOS transistor 10.
One drawback to the use of the source-follower circuit of FIG. 1 for DRAM data retention time measurement, however, is that the RC delay caused by the load resistor 12 considerably affects the accuracy of the measurement.
Moreover, it is highly difficult to obtain the V.sub.out -V.sub.in characteristic of the source-follower circuit with respect to the load resistor 12; therefore, the use of the source-follower circuit of FIG. 1 makes the testkey design very difficult to implement.
In DRAMs, leakage current from the capacitor is the major cause of a low data retention time. The information about the length of the data retention time of a DRAM device is therefore an important factor by which the reliability of the DRAM is evaluated.
The measurement for DRAM data retention time is typically taken during the test phase of the DRAM product. However, it is usually desirable that the measurement be taken during the WAT test so that any DRAM device with a low data retention time can be found early for correction by the fabrication engineers.
Moreover, for a DRAM cell whose capacitor is based on a deep-trench (DT) structure, the knowledge of the data retention time can help the design to reduce the leakage current from the capacitor. When the DRAM cell is downsized, i.e., when the DT structure and NO film in the capacitor are reduced in size, the modeling for leakage current and retention time becomes more critical. In this case, the measurement can be restricted by the capacity for bonding pads and parasitic capacitance in the DRAM chip.
FIG. 2A is a schematic, cross-sectional diagram showing the semiconductor structure of a conventional DRAM cell, and FIG. 2B is a schematic diagram showing the equivalent circuit structure of the DRAM cell of FIG. 2A.
As shown, the DRAM cell 20 includes an NMOS transistor 22 and a data-storage capacitor 24. An equivalent resistor 26 is formed from the combination of the deep-trench resistor RDT and the buried-strap resistor RBS between the NMOS transistor 22 and the capacitor 24. A contact resistor RCB 28 is formed between the drain of the NMOS transistor 22 and the bit line VBL. Furthermore, the capacitor 24 is connected to a buried-plate voltage VBP.
There exist two kinds of leakage currents in the DRAM cell 20: one is the reverse current at the buried PN junction, and the other is the leakage current from the deep-trench NO film. These two kinds of leakage currents significantly reduce the data retention time of the DRAM cell 20.
A conventional method for measuring the data retention time of a DRAM cell is to measure the voltage changes at the node SN between the capacitor 24 and the source of the NMOS transistor 22, which indicates the changes of the voltage across the capacitor 24. One drawback to this method, however, is that the accuracy of the measurement is affected by the parasitic capacitance in the DRAM cell 20.